The present invention relates generally to electronic circuit design. More particularly, the present invention relates to driver circuits for a switching circuit having two transistors in a half-bridge configuration.
A half-bridge circuit has two transistors stacked vertically between a power terminal and a ground terminal. The half-bridge configuration can be used for a variety of applications such as DC-DC converters, DC-AC converters AC-DC power supplies, motor controls Class-D power amplifiers etc. A half-bridge configuration in a power converter often has a high-side N-channel MOSFET and a low-side N-channel MOSFET connected at a common node. If both of the N-channel MOSFETs are turned on simultaneously, a shoot-through current will flow from supply to ground, which may be large enough to damage the MOSFETS. Therefore, a delay time is usually introduced after the first MOSFET is turned off and before the second MOSFET is turned on. This time period is known as the dead-time, during which neither the high-side MOSFET nor the low-side MOSFET is turned on. However, if the dead-time is too long, it can degrade the power efficiency, and it can also introduce a large reverse recovery current that also degrades the performance of the circuit. Therefore, it is desirable to optimize the dead-time control under a wide range of process, voltage and temperature variation.
Conventional dead-time control techniques have been proposed. In a first method, a fixed dead-time is inserted to cause a fixed delay between the turn-off of one transistor and the turn-on of the second transistor. Another dead-time control method uses two separate comparators to continuously compare the gate voltages of both transistors to two predetermined voltages, and a control unit uses the results from the comparators to adjust the dead-time.
However, these conventional dead-time control methods suffer from many limitations. More details of these and other limitations are described below.